BEGIN:VCALENDAR VERSION:2.0 PRODID:-//Pentabarf//Schedule 0.3//EN CALSCALE:GREGORIAN METHOD:PUBLISH X-WR-CALDESC;VALUE=TEXT:RISC-V devroom X-WR-CALNAME;VALUE=TEXT:RISC-V devroom X-WR-TIMEZONE;VALUE=TEXT:Europe/Brussels BEGIN:VEVENT METHOD:PUBLISH UID:8381@FOSDEM19@fosdem.org TZID:Europe-Brussels DTSTART:20190202T103000 DTEND:20190202T111500 SUMMARY:LLVM+Clang for RISC-V DESCRIPTION:
This talk will give an update on the journey towards upstream, production-ready support for RISC-V in LLVM, Clang, and related projects. It will detail the project's start, current status, and next steps with a special focus on the work for support for building 64-bit Linux binaries (hard-float ABI, TLS, PIC etc.
CLASS:PUBLIC STATUS:CONFIRMED CATEGORIES:RISC-V URL:https:/fosdem.org/2019/schedule/2019/schedule/event/riscvllvmclang/ LOCATION:AW1.126 ATTENDEE;ROLE=REQ-PARTICIPANT;CUTYPE=INDIVIDUAL;CN="Alex Bradbury":invalid:nomail END:VEVENT BEGIN:VEVENT METHOD:PUBLISH UID:8483@FOSDEM19@fosdem.org TZID:Europe-Brussels DTSTART:20190202T113000 DTEND:20190202T123000 SUMMARY:Porting Debian to the RISC-V architecture DESCRIPTION:The talk tells the story of how the Debian GNU/Linux port for the RISC-V architecture came to life and describes the steps and challenges involved in adding support for a completely new architecture to one of the major Linux distributions. It provides an overview of the current state of the port and gives an outlook on further developments.
CLASS:PUBLIC STATUS:CONFIRMED CATEGORIES:RISC-V URL:https:/fosdem.org/2019/schedule/2019/schedule/event/riscvdebian/ LOCATION:AW1.126 ATTENDEE;ROLE=REQ-PARTICIPANT;CUTYPE=INDIVIDUAL;CN="K. Merker":invalid:nomail END:VEVENT BEGIN:VEVENT METHOD:PUBLISH UID:8181@FOSDEM19@fosdem.org TZID:Europe-Brussels DTSTART:20190202T123000 DTEND:20190202T131500 SUMMARY:The future of Supervisor Binary Interface(SBI) DESCRIPTION:Supervisor Binary Interface (SBI) is one of the most fundamentalinterfaces in RISC-V eco-system. It allows the operating system tointeract with the supervisor execution environment (SEE). The SEE alwaysruns in higher privileged mode than the supervisor OS. It can bea simple bootloader in low-end hardware platform, a hypervisor-providedvirtual machine in a high-end server, or simply machine mode software inbare metal systems. An unchecked rapid development of many RISC-V systemscould lead to incompatibilities between different systems SEE, preventingthe use of a common OS binary image.
The RISC-V ISA has defined SBI to provide a cleaner interface for thesupervisor OS which makes virtualization and bring-up of new hardwareplatforms much easier. In hypervisor extended supervisor (HS) mode, an OS orhypervisor interacts with the machine through the same SBI as an OSnormally does from supervisor mode. An HS-mode hypervisor is expected toimplement the SBI for its virtualized supervisor (VS) mode guest. Thecurrent RISC-V SBI only defines a few mandatory functions such asinter-processor interrupts (IPI) interface, reprogramming timer, serialconsole, and memory barrier instructions. Many important functionalitiessuch as CPU/system power management are not yet defined due todifficulties in accommodating modifications without breaking backwardcompatibility with the current interface.
This talk presents the ongoing work to make SBI an extensible yet robustspecification. The proposal to extend SBI is based on the foundationpolicy of RISC-V i.e. modularity and openness. It will always bebackward compatible with previous versions including the existing akalegacy version. To achieve that, the focus will be only to develop aBase SBI extension that will contain feature list, version and vendortype queries. Once that is ratified, the future extension such asCPU/system power management, vendor extensions can be developed inparallel. The use cases and calling convention of these extensions willbe discussed in details. We will also talk about a referenceimplementation i.e. OpenSBI for the SBI specification. This project willbe licensed under most permissive software license which will alloweverybody to reuse the OpenSBI code base in their favorite softwareeco-system in whatever way choose to do so. This will help in reducingSBI fragmentation in future as well.
In the spirit of the open design nature of RISC-V, the goal of thispresentation is to continue the open discussion leading to theformalizing RISC-V SBI specification simplifying both hardware andsoftware designs and doing so, contributing to further development ofthe RISC-V ecosystem.
CLASS:PUBLIC STATUS:CONFIRMED CATEGORIES:RISC-V URL:https:/fosdem.org/2019/schedule/2019/schedule/event/riscvsbi/ LOCATION:AW1.126 ATTENDEE;ROLE=REQ-PARTICIPANT;CUTYPE=INDIVIDUAL;CN="Atish Patra":invalid:nomail END:VEVENT BEGIN:VEVENT METHOD:PUBLISH UID:8028@FOSDEM19@fosdem.org TZID:Europe-Brussels DTSTART:20190202T133000 DTEND:20190202T141500 SUMMARY:Alternative languages for safe and secure RISC-V programming DESCRIPTION:In this talk I want to open a window into the wonderful world of "alternative"programming languages for RISC-V. What can you get by looking beyond C/C++.
So I will start with a quick introduction to the Ada and SPARK languages, thebenefits, the hurdles. I will also present an overview of the applications anddomains where they shine, when failure is not an option.
I will then do a short getting started session and provide all the details foryou to start RISC-V programming with Ada/SPARK on different platforms (QEMU,HiFive1, FPGAs with PicoRV32).
At the end of the talk, I will give my view of the RISC-V architecture andcommunity from the perspective of an alternative languages developer. I willcover the good points, the risks, and provide some ideas on how the RISC-V cankeep the door open.
CLASS:PUBLIC STATUS:CONFIRMED CATEGORIES:RISC-V URL:https:/fosdem.org/2019/schedule/2019/schedule/event/riscvadaspark/ LOCATION:AW1.126 ATTENDEE;ROLE=REQ-PARTICIPANT;CUTYPE=INDIVIDUAL;CN="Fabien Chouteau":invalid:nomail END:VEVENT BEGIN:VEVENT METHOD:PUBLISH UID:8313@FOSDEM19@fosdem.org TZID:Europe-Brussels DTSTART:20190202T141500 DTEND:20190202T144500 SUMMARY:How compact is compiled RISC-V code? DESCRIPTION:RISC-V is an increasingly popular architecture for embedded systems. For such systems, compiled code density is a critical factor, particularly for deeply embedded and low power systems, where memory may be veryconstrained. Architectures in this space are often designed to improve code density. Thus ARM has its Thumb-2 instructions and RISC-V has its compressed instructions.
If compiler tool chains are to generate compact code, we need to be able to measure how well we are doing. In this talk I shall present measurements of code density for 32-bit RISC-V, ARM and ARC architectures using the GCC and Clang/LLVM compiler tool chains using the BEEBS benchmark suite for deeply embedded systems (http://beebs.eu/). I shall show how confounding factors (such as emulation library implementation and C run-time startup) can be eliminated from such measurements, to ensure the results are meaningful.
The purpose of this exercise is not to show that any one architecture is "best" but to provide insight which will drive compiler optimization for code density. I shall use the data to highlight areas where the RISC-V compiler tool chain can be improved, drawing on customer work carried out by Embecosm during 2018.
CLASS:PUBLIC STATUS:CONFIRMED CATEGORIES:RISC-V URL:https:/fosdem.org/2019/schedule/2019/schedule/event/riscvcompact/ LOCATION:AW1.126 ATTENDEE;ROLE=REQ-PARTICIPANT;CUTYPE=INDIVIDUAL;CN="Jeremy Bennett":invalid:nomail END:VEVENT BEGIN:VEVENT METHOD:PUBLISH UID:8888@FOSDEM19@fosdem.org TZID:Europe-Brussels DTSTART:20190202T144500 DTEND:20190202T151500 SUMMARY:FreeRTOS on RISC-V DESCRIPTION:The open source (now MIT licensed) FreeRTOS kernel has been helping embedded developers manage the complexity of their microcontroller designs for 15 years – during which time FreeRTOS has gained a reputation for reliability, ease of use, and responsive support. FreeRTOS now runs on RISC-V! In this talk you will see how easy it it to execute the FreeRTOS kernel in open source RISC-V emulators and on physical RISC-V microcontrollers, as well as learn how to port the FreeRTOS kernel to new RISC-V implementations.
CLASS:PUBLIC STATUS:CONFIRMED CATEGORIES:RISC-V URL:https:/fosdem.org/2019/schedule/2019/schedule/event/riscvfreertos/ LOCATION:AW1.126 ATTENDEE;ROLE=REQ-PARTICIPANT;CUTYPE=INDIVIDUAL;CN="Richard Barry":invalid:nomail END:VEVENT BEGIN:VEVENT METHOD:PUBLISH UID:8546@FOSDEM19@fosdem.org TZID:Europe-Brussels DTSTART:20190202T153000 DTEND:20190202T161500 SUMMARY:Lessons learned from porting HelenOS to RISC-V DESCRIPTION:HelenOS is an open source operating system based on the microkernel multiserver design principles. One of its goals is to provide excellent target platform portability. From the time of its inception, HelenOS already supported 4 different hardware platforms and currently it supports platforms as diverse as x86, SPARCv9 and ARM. This talk presents practical experiences and lessons learned from porting HelenOS to RISC-V.
CLASS:PUBLIC STATUS:CONFIRMED CATEGORIES:RISC-V URL:https:/fosdem.org/2019/schedule/2019/schedule/event/riscvhelenos/ LOCATION:AW1.126 ATTENDEE;ROLE=REQ-PARTICIPANT;CUTYPE=INDIVIDUAL;CN="Martin Děcký":invalid:nomail END:VEVENT BEGIN:VEVENT METHOD:PUBLISH UID:8183@FOSDEM19@fosdem.org TZID:Europe-Brussels DTSTART:20190202T161500 DTEND:20190202T170000 SUMMARY:Updates from the RISC-V TEE Group DESCRIPTION:In this talk, I'll try to provide an overview of the RISC-V Trusted Execution Environment working group, and what we are working on.
CLASS:PUBLIC STATUS:CONFIRMED CATEGORIES:RISC-V URL:https:/fosdem.org/2019/schedule/2019/schedule/event/riscvtee/ LOCATION:AW1.126 ATTENDEE;ROLE=REQ-PARTICIPANT;CUTYPE=INDIVIDUAL;CN="Nick Kossifidis":invalid:nomail END:VEVENT BEGIN:VEVENT METHOD:PUBLISH UID:8264@FOSDEM19@fosdem.org TZID:Europe-Brussels DTSTART:20190202T171500 DTEND:20190202T180000 SUMMARY:Using SAIL to generate GNU assembler/disassembler and simulator for RISC-V DESCRIPTION:At the GNU Tools Cauldron, my colleague, Jeremy Bennett, showed how thelong established GNU tool, CGEN, can be used to create an assembler,disassembler and simulator from a semi-formal description of the RISC-Varchitecture in Scheme (https://gcc.gnu.org/wiki/cauldron2018#cgen).
However the CGEN specification in Scheme is far from rigorous by today'sstandards. Alastair Reid of ARM has shown how SAIL can be used todefine rigorous semantics for RISC-V in a paper to be presented at POPLin January 2019 (https://alastairreid.github.io/papers/POPL_19/).
In this talk I shall show how a SAIL specification can be transformedinto a CGEN framework. Using this approach, a rigorous SAIL semanticspecification can be used to generate a practical GNU assembler,disassembler and simulator.
This will is a work in progress - the project is not due to finish untilMay 2019. I shall explore the general approach used, and the areas wherethe greater rigour of SAIL runs into problems with the limitations ofCGEN Scheme specification.
CLASS:PUBLIC STATUS:CONFIRMED CATEGORIES:RISC-V URL:https:/fosdem.org/2019/schedule/2019/schedule/event/riscvsail/ LOCATION:AW1.126 ATTENDEE;ROLE=REQ-PARTICIPANT;CUTYPE=INDIVIDUAL;CN="Mary Bennett":invalid:nomail END:VEVENT BEGIN:VEVENT METHOD:PUBLISH UID:8238@FOSDEM19@fosdem.org TZID:Europe-Brussels DTSTART:20190202T180000 DTEND:20190202T183000 SUMMARY:Buildroot for RISC-V DESCRIPTION:Buildroot is an embedded Linux build system that generates complete system images from source for a wide range of boards and processors. I have recently added support for 64-bit RISC-V to the official Buildroot distribution which make it a viable alternative to other build systems for RISC-V such as Yocto.
During this presentation I will give a brief overview of Buildroot and how it compares to Yocto for those in the audience who are unfamiliar with these systems. In the main part of the talk I will look at the issues relating to the implementation of RISC-V support, based on my experiences. This will include a look at the status of the RISC-V software ecosystem with regard to the selection of a suitable toolchain, C library, kernel and bootloader. I will then run through how to configure and build a minimal system for booting under QEMU. Finally I will consider any further work required to improve Buildroot for RISC-V including the status of 32-bit support.
CLASS:PUBLIC STATUS:CONFIRMED CATEGORIES:RISC-V URL:https:/fosdem.org/2019/schedule/2019/schedule/event/riscvbuildroot/ LOCATION:AW1.126 ATTENDEE;ROLE=REQ-PARTICIPANT;CUTYPE=INDIVIDUAL;CN="Mark Corbin":invalid:nomail END:VEVENT BEGIN:VEVENT METHOD:PUBLISH UID:8958@FOSDEM19@fosdem.org TZID:Europe-Brussels DTSTART:20190202T183000 DTEND:20190202T190000 SUMMARY:Fedora on RISC-V 64-bit DESCRIPTION:The talk provides introduction to Fedora/RISCV bootstrap efforts for the last 2+ years. In addition to that, we will overview our current build infrastructure (powered by Koji), different disk image flavors, setup instructions and differences between upstream Fedora and Fedora/RISCV. We will look into future ideas, short-term plans (tentative) for Fedora 30/Rawhide and general wish-list for RISC-V eco-system.
Share with us what is important for you or/and your company. This will help us to focus our efforts on important parts.
CLASS:PUBLIC STATUS:CONFIRMED CATEGORIES:RISC-V URL:https:/fosdem.org/2019/schedule/2019/schedule/event/riscvfedora/ LOCATION:AW1.126 ATTENDEE;ROLE=REQ-PARTICIPANT;CUTYPE=INDIVIDUAL;CN="David Abdurachmanov":invalid:nomail END:VEVENT END:VCALENDAR