Brussels / 4 & 5 February 2023

schedule

RISC-V devroom

Room: K.4.601
Calendar: iCal, xCal


09 10 11 12 13 14 15 16 17 18
Sunday Self-Hosting (Almost) All The Way Down
A FPGA-based Fedora-capable computer that can rebuild its own bitstream		 QtRVSim—Education from Assembly to Pipeline, Cache Performance, and C Level Programming Porting RISC-V to GNU Guix
A year in review		 Linux on RISC-V
Status and progress of RISC-V support in Gentoo Linux and other Linux distributions		 How to add an GCC builtin to the RISC-V compiler Bringing up the OpenHW Group RISC-V tool chains

Read the Call for Papers at https://lists.fosdem.org/pipermail/fosdem/2022q4/003474.html.

RISC-V (pronounced "RISC-five") is an open CPU instruction set architecture whose specification is available under the CC-BY license. During the last years, the RISC-V ecosystem has grown tremendously and upstream support for the architecture has been included in significant parts of the free-software landscape (e.g. in binutils, gcc, glibc, qemu and Linux). Multiple Linux distributions are working on ports to the RISC-V architecture and the first commercially available linux-capable RISC-V silicon has been presented at FOSDEM 2018.

The FOSDEM RISC-V devroom covers the current developments in open-source soft- and hardware for the RISC-V architecture.

Event Speakers Start End

Sunday
  Self-Hosting (Almost) All The Way Down
A FPGA-based Fedora-capable computer that can rebuild its own bitstream		 Gabriel Somlo 09:00 09:40
  QtRVSim—Education from Assembly to Pipeline, Cache Performance, and C Level Programming Pavel Pisa, Jakub Dupak 09:40 10:20
  Porting RISC-V to GNU Guix
A year in review		 Efraim Flashner 10:20 11:00
  Linux on RISC-V
Status and progress of RISC-V support in Gentoo Linux and other Linux distributions		 Jakov Smolić 11:00 11:40
  How to add an GCC builtin to the RISC-V compiler Nandni Jamnadas 11:40 12:20
  Bringing up the OpenHW Group RISC-V tool chains Jeremy Bennett 12:20 13:00